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dts — rk3399.dtsi
**关键词:**rk3399, rockchip, linux, android, dts. dts — rk3399.dtsi #include <dt-bindings/clock/rk3399-cru.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/power/rk3399-power.h> #include <dt-bindings/soc/rockchip,boot-mode.h> #include <dt-bindings/soc/rockchip-system-status.h> #include <dt-bindings/suspend/rockchip-rk3399.h> #include <dt-bindings/thermal/thermal.h> #include "rk3399-dram-default-timing.dtsi" / { compatible = "rockchip,rk3399"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; aliases { i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; i2c7 = &i2c7; i2c8 = &i2c8; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; serial4 = &uart4; dsi0 = &dsi; dsi1 = &dsi1; }; cpus { #address-cells = <2>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu\_l0>; }; core1 { cpu = <&cpu\_l1>; }; core2 { cpu = <&cpu\_l2>; }; core3 { cpu = <&cpu\_l3>; }; }; cluster1 { core0 { cpu = <&cpu\_b0>; }; core1 { cpu = <&cpu\_b1>; }; }; }; cpu\_l0: cpu@0 { device\_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; #cooling-cells = <2>; /\* min followed by max \*/ clocks = <&cru ARMCLKL>; cpu-idle-states = <&CPU\_SLEEP &CLUSTER\_SLEEP>; dynamic-power-coefficient = <100>; }; cpu\_l1: cpu@1 { device\_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; clocks = <&cru ARMCLKL>; cpu-idle-states = <&CPU\_SLEEP &CLUSTER\_SLEEP>; dynamic-power-coefficient = <100>; }; cpu\_l2: cpu@2 { device\_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; clocks = <&cru ARMCLKL>; cpu-idle-states = <&CPU\_SLEEP &CLUSTER\_SLEEP>; dynamic-power-coefficient = <100>; }; cpu\_l3: cpu@3 { device\_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; clocks = <&cru ARMCLKL>; cpu-idle-states = <&CPU\_SLEEP &CLUSTER\_SLEEP>; dynamic-power-coefficient = <100>; }; cpu\_b0: cpu@100 { device\_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; #cooling-cells = <2>; /\* min followed by max \*/ clocks = <&cru ARMCLKB>; cpu-idle-states = <&CPU\_SLEEP &CLUSTER\_SLEEP>; dynamic-power-coefficient = <436>; }; cpu\_b1: cpu@101 { device\_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x0 0x101>; enable-method = "psci"; clocks = <&cru ARMCLKB>; cpu-idle-states = <&CPU\_SLEEP &CLUSTER\_SLEEP>; dynamic-power-coefficient = <436>; }; idle-states { entry-method = "psci"; CPU\_SLEEP: cpu-sleep { compatible = "arm,idle-state"; local-timer-stop; arm,psci-suspend-param = <0x0010000>; entry-latency-us = <120>; exit-latency-us = <250>; min-residency-us = <900>; }; CLUSTER\_SLEEP: cluster-sleep { compatible = "arm,idle-state"; local-timer-stop; arm,psci-suspend-param = <0x1010000>; entry-latency-us = <400>; exit-latency-us = <500>; min-residency-us = <2000>; }; }; }; pmu\_a53 { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC\_PPI 7 IRQ\_TYPE\_LEVEL\_LOW &ppi\_cluster0>; }; pmu\_a72 { compatible = "arm,cortex-a72-pmu"; interrupts = <GIC\_PPI 7 IRQ\_TYPE\_LEVEL\_LOW &ppi\_cluster1>; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC\_PPI 13 IRQ\_TYPE\_LEVEL\_LOW 0>, <GIC\_PPI 14 IRQ\_TYPE\_LEVEL\_LOW 0>, <GIC\_PPI 11 IRQ\_TYPE\_LEVEL\_LOW 0>, <GIC\_PPI 10 IRQ\_TYPE\_LEVEL\_LOW 0>; }; xin24m: xin24m { compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "xin24m"; #clock-cells = <0>; }; dummy\_cpll: dummy\_cpll { compatible = "fixed-clock"; clock-frequency = <0>; clock-output-names = "dummy\_cpll"; #clock-cells = <0>; }; dummy\_vpll: dummy\_vpll { compatible = "fixed-clock"; clock-frequency = <0>; clock-output-names = "dummy\_vpll"; #clock-cells = <0>; }; amba { compatible = "arm,amba-bus"; #address-cells = <2>; #size-cells = <2>; ranges; dmac\_bus: dma-controller@ff6d0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff6d0000 0x0 0x4000>; interrupts = <GIC\_SPI 5 IRQ\_TYPE\_LEVEL\_HIGH 0>, <GIC\_SPI 6 IRQ\_TYPE\_LEVEL\_HIGH 0>; #dma-cells = <1>; clocks = <&cru ACLK\_DMAC0\_PERILP>; clock-names = "apb\_pclk"; peripherals-req-type-burst; }; dmac\_peri: dma-controller@ff6e0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff6e0000 0x0 0x4000>; interrupts = <GIC\_SPI 7 IRQ\_TYPE\_LEVEL\_HIGH 0>, <GIC\_SPI 8 IRQ\_TYPE\_LEVEL\_HIGH 0>; #dma-cells = <1>; clocks = <&cru ACLK\_DMAC1\_PERILP>; clock-names = "apb\_pclk"; peripherals-req-type-burst; }; }; gmac: ethernet@fe300000 { compatible = "rockchip,rk3399-gmac"; reg = <0x0 0xfe300000 0x0 0x10000>; rockchip,grf = <&grf>; interrupts = <GIC\_SPI 12 IRQ\_TYPE\_LEVEL\_HIGH 0>; interrupt-names = "macirq"; clocks = <&cru SCLK\_MAC>, <&cru SCLK\_MAC\_RX>, <&cru SCLK\_MAC\_TX>, <&cru SCLK\_MACREF>, <&cru SCLK\_MACREF\_OUT>, <&cru ACLK\_GMAC>, <&cru PCLK\_GMAC>; clock-names = "stmmaceth", "mac\_clk\_rx", "mac\_clk\_tx", "clk\_mac\_ref", "clk\_mac\_refout", "aclk\_mac", "pclk\_mac"; resets = <&cru SRST\_A\_GMAC>; reset-names = "stmmaceth"; power-domains = <&power RK3399\_PD\_GMAC>; status = "disabled"; }; sdio0: dwmmc@fe310000 { compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe310000 0x0 0x4000>; interrupts = <GIC\_SPI 64 IRQ\_TYPE\_LEVEL\_HIGH 0>; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK\_SDIO>, <&cru SCLK\_SDIO>, <&cru SCLK\_SDIO\_DRV>, <&cru SCLK\_SDIO\_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; power-domains = <&power RK3399\_PD\_SDIOAUDIO>; status = "disabled"; }; sdmmc: dwmmc@fe320000 { compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe320000 0x0 0x4000>; interrupts = <GIC\_SPI 65 IRQ\_TYPE\_LEVEL\_HIGH 0>; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK\_SDMMC>, <&cru SCLK\_SDMMC>, <&cru SCLK\_SDMMC\_DRV>, <&cru SCLK\_SDMMC\_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; power-domains = <&power RK3399\_PD\_SD>; status = "disabled"; }; sdhci: sdhci@fe330000 { compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; interrupts = <GIC\_SPI 11 IRQ\_TYPE\_LEVEL\_HIGH 0>; arasan,soc-ctl-syscon = <&grf>; assigned-clocks = <&cru SCLK\_EMMC>; assigned-clock-rates = <200000000>; clocks = <&cru SCLK\_EMMC>, <&cru ACLK\_EMMC>; clock-names = "clk\_xin", "clk\_ahb"; clock-output-names = "emmc\_cardclock"; #clock-cells = <0>; phys = <&emmc\_phy>; phy-names = "phy\_arasan"; power-domains = <&power RK3399\_PD\_EMMC>; status = "disabled"; }; usic: usb@fe340000 { compatible = "generic-ehci"; reg = <0x0 0xfe340000 0x0 0x30000>; interrupts = <GIC\_SPI 33 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru HCLK\_HSIC>, <&cru SCLK\_HSICPHY>, <&cru PCLK\_HSICPHY>; clock-names = "hclk\_hsic", "clk\_hsicphy", "pclk\_hsicphy"; rockchip-has-usic; status = "disabled"; }; usb\_host0\_ehci: usb@fe380000 { compatible = "generic-ehci"; reg = <0x0 0xfe380000 0x0 0x20000>; interrupts = <GIC\_SPI 26 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru HCLK\_HOST0>, <&cru HCLK\_HOST0\_ARB>, <&cru SCLK\_USBPHY0\_480M\_SRC>; clock-names = "hclk\_host0", "hclk\_host0\_arb", "usbphy0\_480m"; phys = <&u2phy0\_host>; phy-names = "usb"; power-domains = <&power RK3399\_PD\_PERIHP>; status = "disabled"; }; usb\_host0\_ohci: usb@fe3a0000 { compatible = "generic-ohci"; reg = <0x0 0xfe3a0000 0x0 0x20000>; interrupts = <GIC\_SPI 28 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru HCLK\_HOST0>, <&cru HCLK\_HOST0\_ARB>, <&cru SCLK\_USBPHY0\_480M\_SRC>; clock-names = "hclk\_host0", "hclk\_host0\_arb", "usbphy0\_480m"; phys = <&u2phy0\_host>; phy-names = "usb"; power-domains = <&power RK3399\_PD\_PERIHP>; status = "disabled"; }; usb\_host1\_ehci: usb@fe3c0000 { compatible = "generic-ehci"; reg = <0x0 0xfe3c0000 0x0 0x20000>; interrupts = <GIC\_SPI 30 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru HCLK\_HOST1>, <&cru HCLK\_HOST1\_ARB>, <&cru SCLK\_USBPHY1\_480M\_SRC>; clock-names = "hclk\_host1", "hclk\_host1\_arb", "usbphy1\_480m"; phys = <&u2phy1\_host>; phy-names = "usb"; power-domains = <&power RK3399\_PD\_PERIHP>; status = "disabled"; }; usb\_host1\_ohci: usb@fe3e0000 { compatible = "generic-ohci"; reg = <0x0 0xfe3e0000 0x0 0x20000>; interrupts = <GIC\_SPI 32 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru HCLK\_HOST1>, <&cru HCLK\_HOST1\_ARB>, <&cru SCLK\_USBPHY1\_480M\_SRC>; clock-names = "hclk\_host1", "hclk\_host1\_arb", "usbphy1\_480m"; phys = <&u2phy1\_host>; phy-names = "usb"; power-domains = <&power RK3399\_PD\_PERIHP>; status = "disabled"; }; usbdrd3\_0: usb@fe800000 { compatible = "rockchip,rk3399-dwc3"; clocks = <&cru SCLK\_USB3OTG0\_REF>, <&cru SCLK\_USB3OTG0\_SUSPEND>, <&cru ACLK\_USB3OTG0>, <&cru ACLK\_USB3\_GRF>; clock-names = "ref\_clk", "suspend\_clk", "bus\_clk", "grf\_clk"; power-domains = <&power RK3399\_PD\_USB3>; resets = <&cru SRST\_A\_USB3\_OTG0>; reset-names = "usb3-otg"; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; usbdrd\_dwc3\_0: dwc3@fe800000 { compatible = "snps,dwc3"; reg = <0x0 0xfe800000 0x0 0x100000>; interrupts = <GIC\_SPI 105 IRQ\_TYPE\_LEVEL\_HIGH 0>; dr\_mode = "otg"; phys = <&u2phy0\_otg>, <&tcphy0\_usb3>; phy-names = "usb2-phy", "usb3-phy"; phy\_type = "utmi\_wide"; snps,dis\_enblslpm\_quirk; snps,dis-u2-freeclk-exists-quirk; snps,dis\_u2\_susphy\_quirk; snps,dis-del-phy-power-chg-quirk; snps,tx-ipgap-linecheck-dis-quirk; snps,xhci-slow-suspend-quirk; snps,xhci-trb-ent-quirk; snps,usb3-warm-reset-on-resume-quirk; status = "disabled"; }; }; usbdrd3\_1: usb@fe900000 { compatible = "rockchip,rk3399-dwc3"; clocks = <&cru SCLK\_USB3OTG1\_REF>, <&cru SCLK\_USB3OTG1\_SUSPEND>, <&cru ACLK\_USB3OTG1>, <&cru ACLK\_USB3\_GRF>; clock-names = "ref\_clk", "suspend\_clk", "bus\_clk", "grf\_clk"; power-domains = <&power RK3399\_PD\_USB3>; resets = <&cru SRST\_A\_USB3\_OTG1>; reset-names = "usb3-otg"; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; usbdrd\_dwc3\_1: dwc3@fe900000 { compatible = "snps,dwc3"; reg = <0x0 0xfe900000 0x0 0x100000>; interrupts = <GIC\_SPI 110 IRQ\_TYPE\_LEVEL\_HIGH 0>; dr\_mode = "host"; phys = <&u2phy1\_otg>, <&tcphy1\_usb3>; phy-names = "usb2-phy", "usb3-phy"; phy\_type = "utmi\_wide"; snps,dis\_enblslpm\_quirk; snps,dis-u2-freeclk-exists-quirk; snps,dis\_u2\_susphy\_quirk; snps,dis-del-phy-power-chg-quirk; snps,tx-ipgap-linecheck-dis-quirk; snps,xhci-slow-suspend-quirk; snps,xhci-trb-ent-quirk; snps,usb3-warm-reset-on-resume-quirk; status = "disabled"; }; }; cdn\_dp: dp@fec00000 { compatible = "rockchip,rk3399-cdn-dp"; reg = <0x0 0xfec00000 0x0 0x100000>; interrupts = <GIC\_SPI 9 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru SCLK\_DP\_CORE>, <&cru PCLK\_DP\_CTRL>, <&cru SCLK\_SPDIF\_REC\_DPTX>, <&cru PCLK\_VIO\_GRF>; clock-names = "core-clk", "pclk", "spdif", "grf"; assigned-clocks = <&cru SCLK\_DP\_CORE>; assigned-clock-rates = <100000000>; power-domains = <&power RK3399\_PD\_HDCP>; phys = <&tcphy0\_dp>, <&tcphy1\_dp>; resets = <&cru SRST\_DPTX\_SPDIF\_REC>, <&cru SRST\_P\_UPHY0\_DPTX>, <&cru SRST\_P\_UPHY0\_APB>, <&cru SRST\_DP\_CORE>; reset-names = "spdif", "dptx", "apb", "core"; rockchip,grf = <&grf>; #address-cells = <1>; #size-cells = <0>; #sound-dai-cells = <1>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; dp\_in: port { #address-cells = <1>; #size-cells = <0>; dp\_in\_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb\_out\_dp>; }; dp\_in\_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl\_out\_dp>; }; }; }; }; gic: interrupt-controller@fee00000 { compatible = "arm,gic-v3"; #interrupt-cells = <4>; #address-cells = <2>; #size-cells = <2>; ranges; interrupt-controller; reg = <0x0 0xfee00000 0 0x10000>, /\* GICD \*/ <0x0 0xfef00000 0 0xc0000>, /\* GICR \*/ <0x0 0xfff00000 0 0x10000>, /\* GICC \*/ <0x0 0xfff10000 0 0x10000>, /\* GICH \*/ <0x0 0xfff20000 0 0x10000>; /\* GICV \*/ interrupts = <GIC\_PPI 9 IRQ\_TYPE\_LEVEL\_HIGH 0>; its: interrupt-controller@fee20000 { compatible = "arm,gic-v3-its"; msi-controller; reg = <0x0 0xfee20000 0x0 0x20000>; }; ppi-partitions { ppi\_cluster0: interrupt-partition-0 { affinity = <&cpu\_l0 &cpu\_l1 &cpu\_l2 &cpu\_l3>; }; ppi\_cluster1: interrupt-partition-1 { affinity = <&cpu\_b0 &cpu\_b1>; }; }; }; saradc: saradc@ff100000 { compatible = "rockchip,rk3399-saradc"; reg = <0x0 0xff100000 0x0 0x100>; interrupts = <GIC\_SPI 62 IRQ\_TYPE\_LEVEL\_HIGH 0>; #io-channel-cells = <1>; clocks = <&cru SCLK\_SARADC>, <&cru PCLK\_SARADC>; clock-names = "saradc", "apb\_pclk"; resets = <&cru SRST\_P\_SARADC>; reset-names = "saradc-apb"; status = "disabled"; }; i2c0: i2c@ff3c0000 { compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff3c0000 0x0 0x1000>; clocks = <&pmucru SCLK\_I2C0\_PMU>, <&pmucru PCLK\_I2C0\_PMU>; clock-names = "i2c", "pclk"; interrupts = <GIC\_SPI 57 IRQ\_TYPE\_LEVEL\_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c0\_xfer>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c1: i2c@ff110000 { compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff110000 0x0 0x1000>; clocks = <&cru SCLK\_I2C1>, <&cru PCLK\_I2C1>; clock-names = "i2c", "pclk"; interrupts = <GIC\_SPI 59 IRQ\_TYPE\_LEVEL\_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c1\_xfer>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c2: i2c@ff120000 { compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff120000 0x0 0x1000>; clocks = <&cru SCLK\_I2C2>, <&cru PCLK\_I2C2>; clock-names = "i2c", "pclk"; interrupts = <GIC\_SPI 35 IRQ\_TYPE\_LEVEL\_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c2\_xfer>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c3: i2c@ff130000 { compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff130000 0x0 0x1000>; clocks = <&cru SCLK\_I2C3>, <&cru PCLK\_I2C3>; clock-names = "i2c", "pclk"; interrupts = <GIC\_SPI 34 IRQ\_TYPE\_LEVEL\_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c3\_xfer>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c5: i2c@ff140000 { compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff140000 0x0 0x1000>; clocks = <&cru SCLK\_I2C5>, <&cru PCLK\_I2C5>; clock-names = "i2c", "pclk"; interrupts = <GIC\_SPI 38 IRQ\_TYPE\_LEVEL\_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c5\_xfer>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c6: i2c@ff150000 { compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff150000 0x0 0x1000>; clocks = <&cru SCLK\_I2C6>, <&cru PCLK\_I2C6>; clock-names = "i2c", "pclk"; interrupts = <GIC\_SPI 37 IRQ\_TYPE\_LEVEL\_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c6\_xfer>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c7: i2c@ff160000 { compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff160000 0x0 0x1000>; clocks = <&cru SCLK\_I2C7>, <&cru PCLK\_I2C7>; clock-names = "i2c", "pclk"; interrupts = <GIC\_SPI 36 IRQ\_TYPE\_LEVEL\_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c7\_xfer>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; uart0: serial@ff180000 { compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; reg = <0x0 0xff180000 0x0 0x100>; clocks = <&cru SCLK\_UART0>, <&cru PCLK\_UART0>; clock-names = "baudclk", "apb\_pclk"; interrupts = <GIC\_SPI 99 IRQ\_TYPE\_LEVEL\_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&uart0\_xfer &uart0\_cts &uart0\_rts>; status = "disabled"; }; uart1: serial@ff190000 { compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; reg = <0x0 0xff190000 0x0 0x100>; clocks = <&cru SCLK\_UART1>, <&cru PCLK\_UART1>; clock-names = "baudclk", "apb\_pclk"; interrupts = <GIC\_SPI 98 IRQ\_TYPE\_LEVEL\_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&uart1\_xfer>; status = "disabled"; }; uart2: serial@ff1a0000 { compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; reg = <0x0 0xff1a0000 0x0 0x100>; clocks = <&cru SCLK\_UART2>, <&cru PCLK\_UART2>; clock-names = "baudclk", "apb\_pclk"; interrupts = <GIC\_SPI 100 IRQ\_TYPE\_LEVEL\_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&uart2c\_xfer>; status = "disabled"; }; uart3: serial@ff1b0000 { compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; reg = <0x0 0xff1b0000 0x0 0x100>; clocks = <&cru SCLK\_UART3>, <&cru PCLK\_UART3>; clock-names = "baudclk", "apb\_pclk"; interrupts = <GIC\_SPI 101 IRQ\_TYPE\_LEVEL\_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&uart3\_xfer &uart3\_cts &uart3\_rts>; status = "disabled"; }; spi0: spi@ff1c0000 { compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; reg = <0x0 0xff1c0000 0x0 0x1000>; clocks = <&cru SCLK\_SPI0>, <&cru PCLK\_SPI0>; clock-names = "spiclk", "apb\_pclk"; interrupts = <GIC\_SPI 68 IRQ\_TYPE\_LEVEL\_HIGH 0>; dmas = <&dmac\_peri 10>, <&dmac\_peri 11>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi0\_clk &spi0\_tx &spi0\_rx &spi0\_cs0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi1: spi@ff1d0000 { compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; reg = <0x0 0xff1d0000 0x0 0x1000>; clocks = <&cru SCLK\_SPI1>, <&cru PCLK\_SPI1>; clock-names = "spiclk", "apb\_pclk"; interrupts = <GIC\_SPI 53 IRQ\_TYPE\_LEVEL\_HIGH 0>; dmas = <&dmac\_peri 12>, <&dmac\_peri 13>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi1\_clk &spi1\_tx &spi1\_rx &spi1\_cs0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi2: spi@ff1e0000 { compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; reg = <0x0 0xff1e0000 0x0 0x1000>; clocks = <&cru SCLK\_SPI2>, <&cru PCLK\_SPI2>; clock-names = "spiclk", "apb\_pclk"; interrupts = <GIC\_SPI 52 IRQ\_TYPE\_LEVEL\_HIGH 0>; dmas = <&dmac\_peri 14>, <&dmac\_peri 15>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi2\_clk &spi2\_tx &spi2\_rx &spi2\_cs0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi4: spi@ff1f0000 { compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; reg = <0x0 0xff1f0000 0x0 0x1000>; clocks = <&cru SCLK\_SPI4>, <&cru PCLK\_SPI4>; clock-names = "spiclk", "apb\_pclk"; interrupts = <GIC\_SPI 67 IRQ\_TYPE\_LEVEL\_HIGH 0>; dmas = <&dmac\_peri 18>, <&dmac\_peri 19>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi4\_clk &spi4\_tx &spi4\_rx &spi4\_cs0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi5: spi@ff200000 { compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; reg = <0x0 0xff200000 0x0 0x1000>; clocks = <&cru SCLK\_SPI5>, <&cru PCLK\_SPI5>; clock-names = "spiclk", "apb\_pclk"; interrupts = <GIC\_SPI 132 IRQ\_TYPE\_LEVEL\_HIGH 0>; dmas = <&dmac\_bus 8>, <&dmac\_bus 9>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi5\_clk &spi5\_tx &spi5\_rx &spi5\_cs0>; #address-cells = <1>; #size-cells = <0>; power-domains = <&power RK3399\_PD\_SDIOAUDIO>; status = "disabled"; }; thermal\_zones: thermal-zones { soc\_thermal: soc-thermal { polling-delay-passive = <20>; /\* milliseconds \*/ polling-delay = <1000>; /\* milliseconds \*/ sustainable-power = <1000>; /\* milliwatts \*/ thermal-sensors = <&tsadc 0>; trips { threshold: trip-point-0 { temperature = <70000>; /\* millicelsius \*/ hysteresis = <2000>; /\* millicelsius \*/ type = "passive"; }; target: trip-point-1 { temperature = <85000>; /\* millicelsius \*/ hysteresis = <2000>; /\* millicelsius \*/ type = "passive"; }; soc\_crit: soc-crit { temperature = <115000>; /\* millicelsius \*/ hysteresis = <2000>; /\* millicelsius \*/ type = "critical"; }; }; cooling-maps { map0 { trip = <&target>; cooling-device = <&cpu\_l0 THERMAL\_NO\_LIMIT THERMAL\_NO\_LIMIT>; contribution = <4096>; }; map1 { trip = <&target>; cooling-device = <&cpu\_b0 THERMAL\_NO\_LIMIT THERMAL\_NO\_LIMIT>; contribution = <1024>; }; map2 { trip = <&target>; cooling-device = <&gpu THERMAL\_NO\_LIMIT THERMAL\_NO\_LIMIT>; contribution = <4096>; }; }; }; gpu\_thermal: gpu-thermal { polling-delay-passive = <100>; /\* milliseconds \*/ polling-delay = <1000>; /\* milliseconds \*/ thermal-sensors = <&tsadc 1>; }; }; tsadc: tsadc@ff260000 { compatible = "rockchip,rk3399-tsadc"; reg = <0x0 0xff260000 0x0 0x100>; interrupts = <GIC\_SPI 97 IRQ\_TYPE\_LEVEL\_HIGH 0>; rockchip,grf = <&grf>; clocks = <&cru SCLK\_TSADC>, <&cru PCLK\_TSADC>; clock-names = "tsadc", "apb\_pclk"; assigned-clocks = <&cru SCLK\_TSADC>; assigned-clock-rates = <750000>; resets = <&cru SRST\_TSADC>; reset-names = "tsadc-apb"; pinctrl-names = "init", "default", "sleep"; pinctrl-0 = <&otp\_gpio>; pinctrl-1 = <&otp\_out>; pinctrl-2 = <&otp\_gpio>; #thermal-sensor-cells = <1>; rockchip,hw-tshut-temp = <120000>; status = "disabled"; }; qos\_emmc: qos@ffa58000 { compatible = "syscon"; reg = <0x0 0xffa58000 0x0 0x20>; }; qos\_gmac: qos@ffa5c000 { compatible = "syscon"; reg = <0x0 0xffa5c000 0x0 0x20>; }; qos\_pcie: qos@ffa60080 { compatible = "syscon"; reg = <0x0 0xffa60080 0x0 0x20>; }; qos\_usb\_host0: qos@ffa60100 { compatible = "syscon"; reg = <0x0 0xffa60100 0x0 0x20>; }; qos\_usb\_host1: qos@ffa60180 { compatible = "syscon"; reg = <0x0 0xffa60180 0x0 0x20>; }; qos\_usb\_otg0: qos@ffa70000 { compatible = "syscon"; reg = <0x0 0xffa70000 0x0 0x20>; }; qos\_usb\_otg1: qos@ffa70080 { compatible = "syscon"; reg = <0x0 0xffa70080 0x0 0x20>; }; qos\_sd: qos@ffa74000 { compatible = "syscon"; reg = <0x0 0xffa74000 0x0 0x20>; }; qos\_sdioaudio: qos@ffa76000 { compatible = "syscon"; reg = <0x0 0xffa76000 0x0 0x20>; }; qos\_hdcp: qos@ffa90000 { compatible = "syscon"; reg = <0x0 0xffa90000 0x0 0x20>; }; qos\_iep: qos@ffa98000 { compatible = "syscon"; reg = <0x0 0xffa98000 0x0 0x20>; }; qos\_isp0\_m0: qos@ffaa0000 { compatible = "syscon"; reg = <0x0 0xffaa0000 0x0 0x20>; }; qos\_isp0\_m1: qos@ffaa0080 { compatible = "syscon"; reg = <0x0 0xffaa0080 0x0 0x20>; }; qos\_isp1\_m0: qos@ffaa8000 { compatible = "syscon"; reg = <0x0 0xffaa8000 0x0 0x20>; }; qos\_isp1\_m1: qos@ffaa8080 { compatible = "syscon"; reg = <0x0 0xffaa8080 0x0 0x20>; }; qos\_rga\_r: qos@ffab0000 { compatible = "syscon"; reg = <0x0 0xffab0000 0x0 0x20>; }; qos\_rga\_w: qos@ffab0080 { compatible = "syscon"; reg = <0x0 0xffab0080 0x0 0x20>; }; qos\_video\_m0: qos@ffab8000 { compatible = "syscon"; reg = <0x0 0xffab8000 0x0 0x20>; }; qos\_video\_m1\_r: qos@ffac0000 { compatible = "syscon"; reg = <0x0 0xffac0000 0x0 0x20>; }; qos\_video\_m1\_w: qos@ffac0080 { compatible = "syscon"; reg = <0x0 0xffac0080 0x0 0x20>; }; qos\_vop\_big\_r: qos@ffac8000 { compatible = "syscon"; reg = <0x0 0xffac8000 0x0 0x20>; }; qos\_vop\_big\_w: qos@ffac8080 { compatible = "syscon"; reg = <0x0 0xffac8080 0x0 0x20>; }; qos\_vop\_little: qos@ffad0000 { compatible = "syscon"; reg = <0x0 0xffad0000 0x0 0x20>; }; qos\_perihp: qos@ffad8080 { compatible = "syscon"; reg = <0x0 0xffad8080 0x0 0x20>; }; qos\_gpu: qos@ffae0000 { compatible = "syscon"; reg = <0x0 0xffae0000 0x0 0x20>; }; pmu: power-management@ff310000 { compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; reg = <0x0 0xff310000 0x0 0x1000>; /\* \* Note: RK3399 supports 6 voltage domains including VD\_CORE\_L, \* VD\_CORE\_B, VD\_CENTER, VD\_GPU, VD\_LOGIC and VD\_PMU. \* Some of the power domains are grouped together for every \* voltage domain. \* The detail contents as below. \*/ power: power-controller { compatible = "rockchip,rk3399-power-controller"; #power-domain-cells = <1>; #address-cells = <1>; #size-cells = <0>; /\* These power domains are grouped by VD\_CENTER \*/ pd\_iep@RK3399\_PD\_IEP { reg = <RK3399\_PD\_IEP>; clocks = <&cru ACLK\_IEP>, <&cru HCLK\_IEP>; pm\_qos = <&qos\_iep>; }; pd\_rga@RK3399\_PD\_RGA { reg = <RK3399\_PD\_RGA>; clocks = <&cru ACLK\_RGA>, <&cru HCLK\_RGA>; pm\_qos = <&qos\_rga\_r>, <&qos\_rga\_w>; }; pd\_vcodec@RK3399\_PD\_VCODEC { reg = <RK3399\_PD\_VCODEC>; clocks = <&cru ACLK\_VCODEC>, <&cru HCLK\_VCODEC>; pm\_qos = <&qos\_video\_m0>; }; pd\_vdu@RK3399\_PD\_VDU { reg = <RK3399\_PD\_VDU>; clocks = <&cru ACLK\_VDU>, <&cru HCLK\_VDU>; pm\_qos = <&qos\_video\_m1\_r>, <&qos\_video\_m1\_w>; }; /\* These power domains are grouped by VD\_GPU \*/ pd\_gpu@RK3399\_PD\_GPU { reg = <RK3399\_PD\_GPU>; clocks = <&cru ACLK\_GPU>; pm\_qos = <&qos\_gpu>; }; /\* These power domains are grouped by VD\_LOGIC \*/ pd\_edp@RK3399\_PD\_EDP { reg = <RK3399\_PD\_EDP>; clocks = <&cru PCLK\_EDP\_CTRL>; }; pd\_emmc@RK3399\_PD\_EMMC { reg = <RK3399\_PD\_EMMC>; clocks = <&cru ACLK\_EMMC>; pm\_qos = <&qos\_emmc>; }; pd\_gmac@RK3399\_PD\_GMAC { reg = <RK3399\_PD\_GMAC>; clocks = <&cru ACLK\_GMAC>, <&cru PCLK\_GMAC>; pm\_qos = <&qos\_gmac>; }; pd\_perihp@RK3399\_PD\_PERIHP { reg = <RK3399\_PD\_PERIHP>; #address-cells = <1>; #size-cells = <0>; clocks = <&cru ACLK\_PERIHP>; pm\_qos = <&qos\_perihp>, <&qos\_pcie>, <&qos\_usb\_host0>, <&qos\_usb\_host1>; pd\_sd@RK3399\_PD\_SD { reg = <RK3399\_PD\_SD>; clocks = <&cru HCLK\_SDMMC>, <&cru SCLK\_SDMMC>; pm\_qos = <&qos\_sd>; }; }; pd\_sdioaudio@RK3399\_PD\_SDIOAUDIO { reg = <RK3399\_PD\_SDIOAUDIO>; clocks = <&cru HCLK\_SDIO>; pm\_qos = <&qos\_sdioaudio>; }; pd\_usb3@RK3399\_PD\_USB3 { reg = <RK3399\_PD\_USB3>; clocks = <&cru ACLK\_USB3>; pm\_qos = <&qos\_usb\_otg0>, <&qos\_usb\_otg1>; }; pd\_vio@RK3399\_PD\_VIO { reg = <RK3399\_PD\_VIO>; #address-cells = <1>; #size-cells = <0>; pd\_hdcp@RK3399\_PD\_HDCP { reg = <RK3399\_PD\_HDCP>; clocks = <&cru ACLK\_HDCP>, <&cru HCLK\_HDCP>, <&cru PCLK\_HDCP>; pm\_qos = <&qos\_hdcp>; }; pd\_isp0@RK3399\_PD\_ISP0 { reg = <RK3399\_PD\_ISP0>; clocks = <&cru ACLK\_ISP0>, <&cru HCLK\_ISP0>; pm\_qos = <&qos\_isp0\_m0>, <&qos\_isp0\_m1>; }; pd\_isp1@RK3399\_PD\_ISP1 { reg = <RK3399\_PD\_ISP1>; clocks = <&cru ACLK\_ISP1>, <&cru HCLK\_ISP1>; pm\_qos = <&qos\_isp1\_m0>, <&qos\_isp1\_m1>; }; pd\_tcpc0@RK3399\_PD\_TCPC0 { reg = <RK3399\_PD\_TCPD0>; clocks = <&cru SCLK\_UPHY0\_TCPDCORE>, <&cru SCLK\_UPHY0\_TCPDPHY\_REF>; }; pd\_tcpc1@RK3399\_PD\_TCPC1 { reg = <RK3399\_PD\_TCPD1>; clocks = <&cru SCLK\_UPHY1\_TCPDCORE>, <&cru SCLK\_UPHY1\_TCPDPHY\_REF>; }; pd\_vo@RK3399\_PD\_VO { reg = <RK3399\_PD\_VO>; #address-cells = <1>; #size-cells = <0>; pd\_vopb@RK3399\_PD\_VOPB { reg = <RK3399\_PD\_VOPB>; clocks = <&cru ACLK\_VOP0>, <&cru HCLK\_VOP0>; pm\_qos = <&qos\_vop\_big\_r>, <&qos\_vop\_big\_w>; }; pd\_vopl@RK3399\_PD\_VOPL { reg = <RK3399\_PD\_VOPL>; clocks = <&cru ACLK\_VOP1>, <&cru HCLK\_VOP1>; pm\_qos = <&qos\_vop\_little>; }; }; }; }; }; pmugrf: syscon@ff320000 { compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff320000 0x0 0x1000>; #address-cells = <1>; #size-cells = <1>; pmu\_io\_domains: io-domains { compatible = "rockchip,rk3399-pmu-io-voltage-domain"; status = "disabled"; }; reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x300>; mode-bootloader = <BOOT\_BL\_DOWNLOAD>; mode-charge = <BOOT\_CHARGING>; mode-fastboot = <BOOT\_FASTBOOT>; mode-loader = <BOOT\_BL\_DOWNLOAD>; mode-normal = <BOOT\_NORMAL>; mode-recovery = <BOOT\_RECOVERY>; mode-ums = <BOOT\_UMS>; }; pmu\_pvtm: pmu-pvtm { compatible = "rockchip,rk3399-pmu-pvtm"; clocks = <&pmucru SCLK\_PVTM\_PMU>; clock-names = "pmu"; resets = <&cru SRST\_PVTM>; reset-names = "pmu"; status = "disabled"; }; }; spi3: spi@ff350000 { compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; reg = <0x0 0xff350000 0x0 0x1000>; clocks = <&pmucru SCLK\_SPI3\_PMU>, <&pmucru PCLK\_SPI3\_PMU>; clock-names = "spiclk", "apb\_pclk"; interrupts = <GIC\_SPI 60 IRQ\_TYPE\_LEVEL\_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi3\_clk &spi3\_tx &spi3\_rx &spi3\_cs0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; uart4: serial@ff370000 { compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; reg = <0x0 0xff370000 0x0 0x100>; clocks = <&pmucru SCLK\_UART4\_PMU>, <&pmucru PCLK\_UART4\_PMU>; clock-names = "baudclk", "apb\_pclk"; interrupts = <GIC\_SPI 102 IRQ\_TYPE\_LEVEL\_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&uart4\_xfer>; status = "disabled"; }; i2c4: i2c@ff3d0000 { compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff3d0000 0x0 0x1000>; clocks = <&pmucru SCLK\_I2C4\_PMU>, <&pmucru PCLK\_I2C4\_PMU>; clock-names = "i2c", "pclk"; interrupts = <GIC\_SPI 56 IRQ\_TYPE\_LEVEL\_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c4\_xfer>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c8: i2c@ff3e0000 { compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff3e0000 0x0 0x1000>; clocks = <&pmucru SCLK\_I2C8\_PMU>, <&pmucru PCLK\_I2C8\_PMU>; clock-names = "i2c", "pclk"; interrupts = <GIC\_SPI 58 IRQ\_TYPE\_LEVEL\_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c8\_xfer>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; pcie\_phy: pcie-phy { compatible = "rockchip,rk3399-pcie-phy"; #phy-cells = <0>; rockchip,grf = <&grf>; clocks = <&cru SCLK\_PCIEPHY\_REF>; clock-names = "refclk"; resets = <&cru SRST\_PCIEPHY>; reset-names = "phy"; status = "disabled"; }; pcie0: pcie@f8000000 { compatible = "rockchip,rk3399-pcie"; #address-cells = <3>; #size-cells = <2>; aspm-no-l0s; clocks = <&cru ACLK\_PCIE>, <&cru ACLK\_PERF\_PCIE>, <&cru PCLK\_PCIE>, <&cru SCLK\_PCIE\_PM>; clock-names = "aclk", "aclk-perf", "hclk", "pm"; bus-range = <0x0 0x1f>; max-link-speed = <1>; linux,pci-domain = <0>; msi-map = <0x0 &its 0x0 0x1000>; interrupts = <GIC\_SPI 49 IRQ\_TYPE\_LEVEL\_HIGH 0>, <GIC\_SPI 50 IRQ\_TYPE\_LEVEL\_HIGH 0>, <GIC\_SPI 51 IRQ\_TYPE\_LEVEL\_HIGH 0>; interrupt-names = "sys", "legacy", "client"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie0\_intc 0>, <0 0 0 2 &pcie0\_intc 1>, <0 0 0 3 &pcie0\_intc 2>, <0 0 0 4 &pcie0\_intc 3>; phys = <&pcie\_phy>; phy-names = "pcie-phy"; ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>; reg-names = "axi-base", "apb-base"; resets = <&cru SRST\_PCIE\_CORE>, <&cru SRST\_PCIE\_MGMT>, <&cru SRST\_PCIE\_MGMT\_STICKY>, <&cru SRST\_PCIE\_PIPE>, <&cru SRST\_PCIE\_PM>, <&cru SRST\_P\_PCIE>, <&cru SRST\_A\_PCIE>; reset-names = "core", "mgmt", "mgmt-sticky", "pipe", "pm", "pclk", "aclk"; status = "disabled"; pcie0\_intc: interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; pwm0: pwm@ff420000 { compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; reg = <0x0 0xff420000 0x0 0x10>; #pwm-cells = <3>; pinctrl-names = "active"; pinctrl-0 = <&pwm0\_pin>; clocks = <&pmucru PCLK\_RKPWM\_PMU>; clock-names = "pwm"; status = "disabled"; }; pwm1: pwm@ff420010 { compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; reg = <0x0 0xff420010 0x0 0x10>; #pwm-cells = <3>; pinctrl-names = "active"; pinctrl-0 = <&pwm1\_pin>; clocks = <&pmucru PCLK\_RKPWM\_PMU>; clock-names = "pwm"; status = "disabled"; }; pwm2: pwm@ff420020 { compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; reg = <0x0 0xff420020 0x0 0x10>; #pwm-cells = <3>; pinctrl-names = "active"; pinctrl-0 = <&pwm2\_pin>; clocks = <&pmucru PCLK\_RKPWM\_PMU>; clock-names = "pwm"; status = "disabled"; }; pwm3: pwm@ff420030 { compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; reg = <0x0 0xff420030 0x0 0x10>; #pwm-cells = <3>; pinctrl-names = "active"; pinctrl-0 = <&pwm3a\_pin>; clocks = <&pmucru PCLK\_RKPWM\_PMU>; clock-names = "pwm"; status = "disabled"; }; dfi: dfi@ff630000 { reg = <0x00 0xff630000 0x00 0x4000>; compatible = "rockchip,rk3399-dfi"; rockchip,pmu = <&pmugrf>; clocks = <&cru PCLK\_DDR\_MON>; clock-names = "pclk\_ddr\_mon"; status = "disabled"; }; dmc: dmc { compatible = "rockchip,rk3399-dmc"; devfreq-events = <&dfi>; interrupts = <GIC\_SPI 1 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru SCLK\_DDRCLK>; clock-names = "dmc\_clk"; ddr\_timing = <&ddr\_timing>; upthreshold = <40>; downdifferential = <20>; system-status-freq = < /\*system status freq(KHz)\*/ SYS\_STATUS\_NORMAL 800000 SYS\_STATUS\_REBOOT 528000 SYS\_STATUS\_SUSPEND 200000 SYS\_STATUS\_VIDEO\_1080P 300000 SYS\_STATUS\_VIDEO\_4K 600000 SYS\_STATUS\_VIDEO\_4K\_10B 800000 SYS\_STATUS\_PERFORMANCE 800000 SYS\_STATUS\_BOOST 400000 SYS\_STATUS\_DUALVIEW 600000 SYS\_STATUS\_ISP 600000 >; vop-pn-msch-readlatency = < /\* plane\_number readlatency \*/ 0 0 4 0x20 >; auto-min-freq = <400000>; auto-freq-en = <1>; status = "disabled"; }; vpu: vpu\_service@ff650000 { compatible = "rockchip,vpu\_service"; rockchip,grf = <&grf>; iommus = <&vpu\_mmu>; iommu\_enabled = <1>; reg = <0x0 0xff650000 0x0 0x800>; interrupts = <GIC\_SPI 113 IRQ\_TYPE\_LEVEL\_HIGH 0>, <GIC\_SPI 114 IRQ\_TYPE\_LEVEL\_HIGH 0>; interrupt-names = "irq\_dec", "irq\_enc"; clocks = <&cru ACLK\_VCODEC>, <&cru HCLK\_VCODEC>; clock-names = "aclk\_vcodec", "hclk\_vcodec"; resets = <&cru SRST\_H\_VCODEC>, <&cru SRST\_A\_VCODEC>; reset-names = "video\_h", "video\_a"; power-domains = <&power RK3399\_PD\_VCODEC>; name = "vpu\_service"; dev\_mode = <0>; /\* 0 means ion, 1 means drm \*/ allocator = <1>; status = "disabled"; }; vpu\_mmu: iommu@ff650800 { compatible = "rockchip,iommu"; reg = <0x0 0xff650800 0x0 0x40>; interrupts = <GIC\_SPI 115 IRQ\_TYPE\_LEVEL\_HIGH 0>; interrupt-names = "vpu\_mmu"; clocks = <&cru ACLK\_VCODEC>, <&cru HCLK\_VCODEC>; clock-names = "aclk", "hclk"; power-domains = <&power RK3399\_PD\_VCODEC>; #iommu-cells = <0>; }; rkvdec: rkvdec@ff660000 { compatible = "rockchip,rkvdec"; rockchip,grf = <&grf>; iommus = <&vdec\_mmu>; iommu\_enabled = <1>; reg = <0x0 0xff660000 0x0 0x400>; interrupts = <GIC\_SPI 116 IRQ\_TYPE\_LEVEL\_HIGH 0>; interrupt-names = "irq\_dec"; clocks = <&cru ACLK\_VDU>, <&cru HCLK\_VDU>, <&cru SCLK\_VDU\_CA>, <&cru SCLK\_VDU\_CORE>; clock-names = "aclk\_vcodec", "hclk\_vcodec", "clk\_cabac", "clk\_core"; resets = <&cru SRST\_H\_VDU>, <&cru SRST\_A\_VDU>, <&cru SRST\_VDU\_CORE>, <&cru SRST\_VDU\_CA>, <&cru SRST\_A\_VDU\_NOC>, <&cru SRST\_H\_VDU\_NOC>; reset-names = "video\_h", "video\_a", "video\_core", "video\_cabac", "niu\_a", "niu\_h"; power-domains = <&power RK3399\_PD\_VDU>; dev\_mode = <2>; name = "rkvdec"; /\* 0 means ion, 1 means drm \*/ allocator = <1>; status = "disabled"; }; vdec\_mmu: iommu@ff660480 { compatible = "rockchip,iommu"; reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; interrupts = <GIC\_SPI 117 IRQ\_TYPE\_LEVEL\_HIGH 0>; interrupt-names = "vdec\_mmu"; clocks = <&cru ACLK\_VDU>, <&cru HCLK\_VDU>; clock-names = "aclk", "hclk"; power-domains = <&power RK3399\_PD\_VDU>; #iommu-cells = <0>; }; iep: iep@ff670000 { compatible = "rockchip,iep"; iommu\_enabled = <1>; iommus = <&iep\_mmu>; reg = <0x0 0xff670000 0x0 0x800>; interrupts = <GIC\_SPI 42 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru ACLK\_IEP>, <&cru HCLK\_IEP>; clock-names = "aclk\_iep", "hclk\_iep"; power-domains = <&power RK3399\_PD\_IEP>; allocator = <1>; version = <2>; status = "disabled"; }; iep\_mmu: iommu@ff670800 { compatible = "rockchip,iommu"; reg = <0x0 0xff670800 0x0 0x40>; interrupts = <GIC\_SPI 42 IRQ\_TYPE\_LEVEL\_HIGH 0>; interrupt-names = "iep\_mmu"; #iommu-cells = <0>; status = "disabled"; }; rga: rga@ff680000 { compatible = "rockchip,rk3399-rga"; reg = <0x0 0xff680000 0x0 0x10000>; interrupts = <GIC\_SPI 55 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru ACLK\_RGA>, <&cru HCLK\_RGA>, <&cru SCLK\_RGA\_CORE>; clock-names = "aclk", "hclk", "sclk"; resets = <&cru SRST\_RGA\_CORE>, <&cru SRST\_A\_RGA>, <&cru SRST\_H\_RGA>; reset-names = "core", "axi", "ahb"; power-domains = <&power RK3399\_PD\_RGA>; status = "disabled"; }; efuse0: efuse@ff690000 { compatible = "rockchip,rk3399-efuse"; reg = <0x0 0xff690000 0x0 0x80>; #address-cells = <1>; #size-cells = <1>; clocks = <&cru PCLK\_EFUSE1024NS>; clock-names = "pclk\_efuse"; /\* Data cells \*/ specification\_serial\_number: specification-serial-number@6 { reg = <0x06 0x1>; bits = <0 5>; }; cpu\_id: cpu-id@7 { reg = <0x07 0x10>; }; cpub\_leakage: cpu-leakage@17 { reg = <0x17 0x1>; }; gpu\_leakage: gpu-leakage@18 { reg = <0x18 0x1>; }; center\_leakage: center-leakage@19 { reg = <0x19 0x1>; }; cpul\_leakage: cpu-leakage@1a { reg = <0x1a 0x1>; }; logic\_leakage: logic-leakage@1b { reg = <0x1b 0x1>; }; wafer\_info: wafer-info@1c { reg = <0x1c 0x1>; }; }; pmucru: pmu-clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = <&pmucru PLL\_PPLL>, <&pmucru FCLK\_CM0S\_SRC\_PMU>; assigned-clock-rates = <676000000>, <97000000>; }; cru: clock-controller@ff760000 { compatible = "rockchip,rk3399-cru"; reg = <0x0 0xff760000 0x0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = <&cru ACLK\_VOP0>, <&cru HCLK\_VOP0>, <&cru ACLK\_VOP1>, <&cru HCLK\_VOP1>, <&cru ARMCLKL>, <&cru ARMCLKB>, <&cru PLL\_GPLL>, <&cru PLL\_CPLL>, <&cru ACLK\_GPU>, <&cru PLL\_NPLL>, <&cru ACLK\_PERIHP>, <&cru HCLK\_PERIHP>, <&cru PCLK\_PERIHP>, <&cru ACLK\_PERILP0>, <&cru HCLK\_PERILP0>, <&cru PCLK\_PERILP0>, <&cru HCLK\_PERILP1>, <&cru PCLK\_PERILP1>; assigned-clock-rates = <400000000>, <200000000>, <400000000>, <200000000>, <816000000>, <816000000>, <594000000>, <800000000>, <200000000>, <1000000000>, <150000000>, <75000000>, <37500000>, <100000000>, <100000000>, <50000000>, <100000000>, <50000000>; }; grf: syscon@ff770000 { compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x10000>; #address-cells = <1>; #size-cells = <1>; io\_domains: io-domains { compatible = "rockchip,rk3399-io-voltage-domain"; status = "disabled"; }; emmc\_phy: phy@f780 { compatible = "rockchip,rk3399-emmc-phy"; reg = <0xf780 0x24>; clocks = <&sdhci>; clock-names = "emmcclk"; #phy-cells = <0>; status = "disabled"; }; u2phy0: usb2-phy@e450 { compatible = "rockchip,rk3399-usb2phy"; reg = <0xe450 0x10>; clocks = <&cru SCLK\_USB2PHY0\_REF>; clock-names = "phyclk"; #clock-cells = <0>; clock-output-names = "clk\_usbphy0\_480m"; status = "disabled"; u2phy0\_otg: otg-port { #phy-cells = <0>; interrupts = <GIC\_SPI 103 IRQ\_TYPE\_LEVEL\_HIGH 0>, <GIC\_SPI 104 IRQ\_TYPE\_LEVEL\_HIGH 0>, <GIC\_SPI 106 IRQ\_TYPE\_LEVEL\_HIGH 0>; interrupt-names = "otg-bvalid", "otg-id", "linestate"; status = "disabled"; }; u2phy0\_host: host-port { #phy-cells = <0>; interrupts = <GIC\_SPI 27 IRQ\_TYPE\_LEVEL\_HIGH 0>; interrupt-names = "linestate"; status = "disabled"; }; }; u2phy1: usb2-phy@e460 { compatible = "rockchip,rk3399-usb2phy"; reg = <0xe460 0x10>; clocks = <&cru SCLK\_USB2PHY1\_REF>; clock-names = "phyclk"; #clock-cells = <0>; clock-output-names = "clk\_usbphy1\_480m"; status = "disabled"; u2phy1\_otg: otg-port { #phy-cells = <0>; interrupts = <GIC\_SPI 108 IRQ\_TYPE\_LEVEL\_HIGH 0>, <GIC\_SPI 109 IRQ\_TYPE\_LEVEL\_HIGH 0>, <GIC\_SPI 111 IRQ\_TYPE\_LEVEL\_HIGH 0>; interrupt-names = "otg-bvalid", "otg-id", "linestate"; status = "disabled"; }; u2phy1\_host: host-port { #phy-cells = <0>; interrupts = <GIC\_SPI 31 IRQ\_TYPE\_LEVEL\_HIGH 0>; interrupt-names = "linestate"; status = "disabled"; }; }; mipi\_dphy\_rx0: mipi-dphy-rx0 { compatible = "rockchip,rk3399-mipi-dphy"; clocks = <&cru SCLK\_MIPIDPHY\_REF>, <&cru SCLK\_DPHY\_RX0\_CFG>, <&cru PCLK\_VIO\_GRF>; clock-names = "dphy-ref", "dphy-cfg", "grf"; power-domains = <&power RK3399\_PD\_VIO>; status = "disabled"; }; pvtm: pvtm { compatible = "rockchip,rk3399-pvtm"; clocks = <&cru SCLK\_PVTM\_CORE\_L>, <&cru SCLK\_PVTM\_CORE\_B>, <&cru SCLK\_PVTM\_GPU>, <&cru SCLK\_PVTM\_DDR>; clock-names = "core\_l", "core\_b", "gpu", "ddr"; resets = <&cru SRST\_PVTM\_CORE\_L>, <&cru SRST\_PVTM\_CORE\_B>, <&cru SRST\_PVTM\_GPU>, <&cru SRST\_PVTM\_DDR>; reset-names = "core\_l", "core\_b", "gpu", "ddr"; status = "disabled"; }; }; tcphy0: phy@ff7c0000 { compatible = "rockchip,rk3399-typec-phy"; reg = <0x0 0xff7c0000 0x0 0x40000>; rockchip,grf = <&grf>; #phy-cells = <1>; clocks = <&cru SCLK\_UPHY0\_TCPDCORE>, <&cru SCLK\_UPHY0\_TCPDPHY\_REF>; clock-names = "tcpdcore", "tcpdphy-ref"; assigned-clocks = <&cru SCLK\_UPHY0\_TCPDCORE>; assigned-clock-rates = <50000000>; power-domains = <&power RK3399\_PD\_TCPD0>; resets = <&cru SRST\_UPHY0>, <&cru SRST\_UPHY0\_PIPE\_L00>, <&cru SRST\_P\_UPHY0\_TCPHY>; reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; rockchip,typec-conn-dir = <0xe580 0 16>; rockchip,usb3tousb2-en = <0xe580 3 19>; rockchip,usb3-host-disable = <0x2434 0 16>; rockchip,usb3-host-port = <0x2434 12 28>; rockchip,external-psm = <0xe588 14 30>; rockchip,pipe-status = <0xe5c0 0 0>; rockchip,uphy-dp-sel = <0x6268 19 19>; status = "disabled"; tcphy0\_dp: dp-port { #phy-cells = <0>; }; tcphy0\_usb3: usb3-port { #phy-cells = <0>; }; }; tcphy1: phy@ff800000 { compatible = "rockchip,rk3399-typec-phy"; reg = <0x0 0xff800000 0x0 0x40000>; rockchip,grf = <&grf>; #phy-cells = <1>; clocks = <&cru SCLK\_UPHY1\_TCPDCORE>, <&cru SCLK\_UPHY1\_TCPDPHY\_REF>; clock-names = "tcpdcore", "tcpdphy-ref"; assigned-clocks = <&cru SCLK\_UPHY1\_TCPDCORE>; assigned-clock-rates = <50000000>; power-domains = <&power RK3399\_PD\_TCPD1>; resets = <&cru SRST\_UPHY1>, <&cru SRST\_UPHY1\_PIPE\_L00>, <&cru SRST\_P\_UPHY1\_TCPHY>; reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; rockchip,typec-conn-dir = <0xe58c 0 16>; rockchip,usb3tousb2-en = <0xe58c 3 19>; rockchip,usb3-host-disable = <0x2444 0 16>; rockchip,usb3-host-port = <0x2444 12 28>; rockchip,external-psm = <0xe594 14 30>; rockchip,pipe-status = <0xe5c0 16 16>; rockchip,uphy-dp-sel = <0x6268 3 19>; status = "disabled"; tcphy1\_dp: dp-port { #phy-cells = <0>; }; tcphy1\_usb3: usb3-port { #phy-cells = <0>; }; }; watchdog@ff848000 { compatible = "snps,dw-wdt"; reg = <0x0 0xff848000 0x0 0x100>; clocks = <&cru PCLK\_WDT>; interrupts = <GIC\_SPI 120 IRQ\_TYPE\_LEVEL\_HIGH 0>; }; rktimer: rktimer@ff850000 { compatible = "rockchip,rk3399-timer"; reg = <0x0 0xff850000 0x0 0x1000>; interrupts = <GIC\_SPI 81 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru PCLK\_TIMER0>, <&cru SCLK\_TIMER00>; clock-names = "pclk", "timer"; }; spdif: spdif@ff870000 { compatible = "rockchip,rk3399-spdif"; reg = <0x0 0xff870000 0x0 0x1000>; interrupts = <GIC\_SPI 66 IRQ\_TYPE\_LEVEL\_HIGH 0>; dmas = <&dmac\_bus 7>; dma-names = "tx"; clock-names = "mclk", "hclk"; clocks = <&cru SCLK\_SPDIF\_8CH>, <&cru HCLK\_SPDIF>; pinctrl-names = "default"; pinctrl-0 = <&spdif\_bus>; power-domains = <&power RK3399\_PD\_SDIOAUDIO>; status = "disabled"; }; i2s0: i2s@ff880000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff880000 0x0 0x1000>; rockchip,grf = <&grf>; interrupts = <GIC\_SPI 39 IRQ\_TYPE\_LEVEL\_HIGH 0>; dmas = <&dmac\_bus 0>, <&dmac\_bus 1>; dma-names = "tx", "rx"; clock-names = "i2s\_clk", "i2s\_hclk"; clocks = <&cru SCLK\_I2S0\_8CH>, <&cru HCLK\_I2S0\_8CH>; pinctrl-names = "default"; pinctrl-0 = <&i2s0\_8ch\_bus>; power-domains = <&power RK3399\_PD\_SDIOAUDIO>; status = "disabled"; }; i2s1: i2s@ff890000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff890000 0x0 0x1000>; interrupts = <GIC\_SPI 40 IRQ\_TYPE\_LEVEL\_HIGH 0>; dmas = <&dmac\_bus 2>, <&dmac\_bus 3>; dma-names = "tx", "rx"; clock-names = "i2s\_clk", "i2s\_hclk"; clocks = <&cru SCLK\_I2S1\_8CH>, <&cru HCLK\_I2S1\_8CH>; pinctrl-names = "default"; pinctrl-0 = <&i2s1\_2ch\_bus>; power-domains = <&power RK3399\_PD\_SDIOAUDIO>; status = "disabled"; }; i2s2: i2s@ff8a0000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff8a0000 0x0 0x1000>; interrupts = <GIC\_SPI 41 IRQ\_TYPE\_LEVEL\_HIGH 0>; dmas = <&dmac\_bus 4>, <&dmac\_bus 5>; dma-names = "tx", "rx"; clock-names = "i2s\_clk", "i2s\_hclk"; clocks = <&cru SCLK\_I2S2\_8CH>, <&cru HCLK\_I2S2\_8CH>; power-domains = <&power RK3399\_PD\_SDIOAUDIO>; status = "disabled"; }; gpu: gpu@ff9a0000 { compatible = "arm,malit860", "arm,malit86x", "arm,malit8xx", "arm,mali-midgard"; reg = <0x0 0xff9a0000 0x0 0x10000>; interrupts = <GIC\_SPI 19 IRQ\_TYPE\_LEVEL\_HIGH 0>, <GIC\_SPI 20 IRQ\_TYPE\_LEVEL\_HIGH 0>, <GIC\_SPI 21 IRQ\_TYPE\_LEVEL\_HIGH 0>; interrupt-names = "GPU", "JOB", "MMU"; clocks = <&cru ACLK\_GPU>; clock-names = "clk\_mali"; #cooling-cells = <2>; /\* min followed by max \*/ power-domains = <&power RK3399\_PD\_GPU>; power-off-delay-ms = <200>; status = "disabled"; gpu\_power\_model: power\_model { compatible = "arm,mali-simple-power-model"; static-coefficient = <411000>; dynamic-coefficient = <733>; ts = <32000 4700 (-80) 2>; thermal-zone = "gpu-thermal"; }; }; vopl: vop@ff8f0000 { compatible = "rockchip,rk3399-vop-lit"; reg = <0x0 0xff8f0000 0x0 0x600>, <0x0 0xff8f1c00 0x0 0x200>, <0x0 0xff8f2000 0x0 0x400>; reg-names = "regs", "cabc\_lut", "gamma\_lut"; interrupts = <GIC\_SPI 119 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru ACLK\_VOP1>, <&cru DCLK\_VOP1>, <&cru HCLK\_VOP1>, <&cru DCLK\_VOP1\_DIV>; clock-names = "aclk\_vop", "dclk\_vop", "hclk\_vop", "dclk\_source"; resets = <&cru SRST\_A\_VOP1>, <&cru SRST\_H\_VOP1>, <&cru SRST\_D\_VOP1>; reset-names = "axi", "ahb", "dclk"; power-domains = <&power RK3399\_PD\_VOPL>; iommus = <&vopl\_mmu>; status = "disabled"; vopl\_out: port { #address-cells = <1>; #size-cells = <0>; vopl\_out\_dsi: endpoint@0 { reg = <0>; remote-endpoint = <&dsi\_in\_vopl>; }; vopl\_out\_edp: endpoint@1 { reg = <1>; remote-endpoint = <&edp\_in\_vopl>; }; vopl\_out\_hdmi: endpoint@2 { reg = <2>; remote-endpoint = <&hdmi\_in\_vopl>; }; vopl\_out\_dp: endpoint@3 { reg = <3>; remote-endpoint = <&dp\_in\_vopl>; }; vopl\_out\_dsi1: endpoint@4 { reg = <4>; remote-endpoint = <&dsi1\_in\_vopl>; }; }; }; vop1\_pwm: voppwm@ff8f01a0 { compatible = "rockchip,vop-pwm"; reg = <0x0 0xff8f01a0 0x0 0x10>; #pwm-cells = <3>; pinctrl-names = "active"; pinctrl-0 = <&vop1\_pwm\_pin>; clocks = <&cru SCLK\_VOP1\_PWM>; clock-names = "pwm"; status = "disabled"; }; vopl\_mmu: iommu@ff8f3f00 { compatible = "rockchip,iommu"; reg = <0x0 0xff8f3f00 0x0 0x100>; interrupts = <GIC\_SPI 119 IRQ\_TYPE\_LEVEL\_HIGH 0>; interrupt-names = "vopl\_mmu"; clocks = <&cru ACLK\_VOP1>, <&cru HCLK\_VOP1>; clock-names = "aclk", "hclk"; power-domains = <&power RK3399\_PD\_VOPL>; #iommu-cells = <0>; status = "disabled"; }; vopb: vop@ff900000 { compatible = "rockchip,rk3399-vop-big"; reg = <0x0 0xff900000 0x0 0x600>, <0x0 0xff901c00 0x0 0x200>, <0x0 0xff902000 0x0 0x1000>; reg-names = "regs", "cabc\_lut", "gamma\_lut"; interrupts = <GIC\_SPI 118 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru ACLK\_VOP0>, <&cru DCLK\_VOP0>, <&cru HCLK\_VOP0>, <&cru DCLK\_VOP0\_DIV>; clock-names = "aclk\_vop", "dclk\_vop", "hclk\_vop", "dclk\_source"; resets = <&cru SRST\_A\_VOP0>, <&cru SRST\_H\_VOP0>, <&cru SRST\_D\_VOP0>; reset-names = "axi", "ahb", "dclk"; power-domains = <&power RK3399\_PD\_VOPB>; iommus = <&vopb\_mmu>; status = "disabled"; vopb\_out: port { #address-cells = <1>; #size-cells = <0>; vopb\_out\_edp: endpoint@0 { reg = <0>; remote-endpoint = <&edp\_in\_vopb>; }; vopb\_out\_dsi: endpoint@1 { reg = <1>; remote-endpoint = <&dsi\_in\_vopb>; }; vopb\_out\_hdmi: endpoint@2 { reg = <2>; remote-endpoint = <&hdmi\_in\_vopb>; }; vopb\_out\_dp: endpoint@3 { reg = <3>; remote-endpoint = <&dp\_in\_vopb>; }; vopb\_out\_dsi1: endpoint@4 { reg = <4>; remote-endpoint = <&dsi1\_in\_vopb>; }; }; }; vop0\_pwm: voppwm@ff9001a0 { compatible = "rockchip,vop-pwm"; reg = <0x0 0xff9001a0 0x0 0x10>; #pwm-cells = <3>; pinctrl-names = "active"; pinctrl-0 = <&vop0\_pwm\_pin>; clocks = <&cru SCLK\_VOP0\_PWM>; clock-names = "pwm"; status = "disabled"; }; vopb\_mmu: iommu@ff903f00 { compatible = "rockchip,iommu"; reg = <0x0 0xff903f00 0x0 0x100>; interrupts = <GIC\_SPI 118 IRQ\_TYPE\_LEVEL\_HIGH 0>; interrupt-names = "vopb\_mmu"; clocks = <&cru ACLK\_VOP0>, <&cru HCLK\_VOP0>; clock-names = "aclk", "hclk"; power-domains = <&power RK3399\_PD\_VOPB>; #iommu-cells = <0>; status = "disabled"; }; rkisp1\_0: rkisp1@ff910000 { compatible = "rockchip,rk3399-rkisp1"; reg = <0x0 0xff910000 0x0 0x4000>; interrupts = <GIC\_SPI 43 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru SCLK\_ISP0>, <&cru ACLK\_ISP0>, <&cru HCLK\_ISP0>, <&cru ACLK\_ISP0\_WRAPPER>, <&cru HCLK\_ISP0\_WRAPPER>; clock-names = "clk\_isp", "aclk\_isp", "hclk\_isp", "aclk\_isp\_wrap", "hclk\_isp\_wrap"; devfreq = <&dmc>; power-domains = <&power RK3399\_PD\_ISP0>; iommus = <&isp0\_mmu>; status = "disabled"; }; isp0\_mmu: iommu@ff914000 { compatible = "rockchip,iommu"; reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; interrupts = <GIC\_SPI 43 IRQ\_TYPE\_LEVEL\_HIGH 0>; interrupt-names = "isp0\_mmu"; #iommu-cells = <0>; clocks = <&cru ACLK\_ISP0\_NOC>, <&cru HCLK\_ISP0\_NOC>; clock-names = "aclk", "hclk"; power-domains = <&power RK3399\_PD\_ISP0>; rk\_iommu,disable\_reset\_quirk; status = "disabled"; }; rkisp1\_1: rkisp1@ff920000 { compatible = "rockchip,rk3399-rkisp1"; reg = <0x0 0xff920000 0x0 0x4000>; interrupts = <GIC\_SPI 44 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru SCLK\_ISP1>, <&cru ACLK\_ISP1>, <&cru HCLK\_ISP1>, <&cru ACLK\_ISP1\_WRAPPER>, <&cru HCLK\_ISP1\_WRAPPER>; clock-names = "clk\_isp", "aclk\_isp", "hclk\_isp", "aclk\_isp\_wrap", "hclk\_isp\_wrap"; devfreq = <&dmc>; power-domains = <&power RK3399\_PD\_ISP1>; iommus = <&isp1\_mmu>; status = "disabled"; }; isp1\_mmu: iommu@ff924000 { compatible = "rockchip,iommu"; reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; interrupts = <GIC\_SPI 44 IRQ\_TYPE\_LEVEL\_HIGH 0>; interrupt-names = "isp1\_mmu"; #iommu-cells = <0>; clocks = <&cru ACLK\_ISP1\_NOC>, <&cru HCLK\_ISP1\_NOC>; clock-names = "aclk", "hclk"; power-domains = <&power RK3399\_PD\_ISP1>; rk\_iommu,disable\_reset\_quirk; status = "disabled"; }; hdmi: hdmi@ff940000 { compatible = "rockchip,rk3399-dw-hdmi"; reg = <0x0 0xff940000 0x0 0x20000>; reg-io-width = <4>; rockchip,grf = <&grf>; pinctrl-names = "default"; pinctrl-0 = <&hdmi\_i2c\_xfer>; power-domains = <&power RK3399\_PD\_HDCP>; interrupts = <GIC\_SPI 23 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru PCLK\_HDMI\_CTRL>, <&cru SCLK\_HDMI\_SFR>, <&cru PLL\_VPLL>, <&cru PCLK\_VIO\_GRF>, <&cru SCLK\_HDMI\_CEC>; clock-names = "iahb", "isfr", "vpll", "grf", "cec"; status = "disabled"; ports { hdmi\_in: port { #address-cells = <1>; #size-cells = <0>; hdmi\_in\_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb\_out\_hdmi>; }; hdmi\_in\_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl\_out\_hdmi>; }; }; }; }; dsi: dsi@ff960000 { compatible = "rockchip,rk3399-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x8000>; interrupts = <GIC\_SPI 45 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru SCLK\_DPHY\_PLL>, <&cru PCLK\_MIPI\_DSI0>, <&cru SCLK\_DPHY\_TX0\_CFG>; clock-names = "ref", "pclk", "phy\_cfg"; resets = <&cru SRST\_P\_MIPI\_DSI0>; reset-names = "apb"; power-domains = <&power RK3399\_PD\_VIO>; rockchip,grf = <&grf>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; ports { port { #address-cells = <1>; #size-cells = <0>; dsi\_in\_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb\_out\_dsi>; }; dsi\_in\_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl\_out\_dsi>; }; }; }; }; dsi1: dsi@ff968000 { compatible = "rockchip,rk3399-mipi-dsi"; reg = <0x0 0xff968000 0x0 0x8000>; interrupts = <GIC\_SPI 46 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru SCLK\_DPHY\_PLL>, <&cru PCLK\_MIPI\_DSI1>, <&cru SCLK\_DPHY\_TX1RX1\_CFG>; clock-names = "ref", "pclk", "phy\_cfg"; resets = <&cru SRST\_P\_MIPI\_DSI1>; reset-names = "apb"; power-domains = <&power RK3399\_PD\_VIO>; rockchip,grf = <&grf>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; ports { port { #address-cells = <1>; #size-cells = <0>; dsi1\_in\_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb\_out\_dsi1>; }; dsi1\_in\_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl\_out\_dsi1>; }; }; }; }; edp: edp@ff970000 { compatible = "rockchip,rk3399-edp"; reg = <0x0 0xff970000 0x0 0x8000>; interrupts = <GIC\_SPI 10 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru PCLK\_EDP>, <&cru PCLK\_EDP\_CTRL>; clock-names = "dp", "pclk"; power-domains = <&power RK3399\_PD\_EDP>; resets = <&cru SRST\_P\_EDP\_CTRL>; reset-names = "dp"; rockchip,grf = <&grf>; status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&edp\_hpd>; ports { #address-cells = <1>; #size-cells = <0>; edp\_in: port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; edp\_in\_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb\_out\_edp>; }; edp\_in\_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl\_out\_edp>; }; }; }; }; hdmi\_hdcp2: hdmi-hdcp2@ff988000 { compatible = "rockchip,rk3399-hdmi-hdcp2"; reg = <0x0 0xff988000 0x0 0x2000>; interrupts = <GIC\_SPI 22 IRQ\_TYPE\_LEVEL\_HIGH 0>; clocks = <&cru ACLK\_HDCP22>, <&cru PCLK\_HDCP22>, <&cru HCLK\_HDCP22>; clock-names ="aclk\_hdcp2", "pclk\_hdcp2", "hdcp2\_clk\_hdmi"; status = "disabled"; }; display\_subsystem: display-subsystem { compatible = "rockchip,display-subsystem"; ports = <&vopl\_out>, <&vopb\_out>; clocks = <&cru PLL\_VPLL>, <&cru PLL\_CPLL>; clock-names = "hdmi-tmds-pll", "default-vop-pll"; devfreq = <&dmc>; status = "disabled"; }; nocp\_cci\_msch0: nocp-cci-msch0@ffa86000 { compatible = "rockchip,rk3399-nocp"; reg = <0x0 0xffa86000 0x0 0x400>; }; nocp\_gpu\_msch0: nocp-gpu-msch0@ffa86400 { compatible = "rockchip,rk3399-nocp"; reg = <0x0 0xffa86400 0x0 0x400>; }; nocp\_hp\_msch0: nocp-hp-msch0@ffa86800 { compatible = "rockchip,rk3399-nocp"; reg = <0x0 0xffa86800 0x0 0x400>; }; nocp\_lp\_msch0: nocp-lp-msch0@ffa86c00 { compatible = "rockchip,rk3399-nocp"; reg = <0x0 0xffa86c00 0x0 0x400>; }; nocp\_video\_msch0: nocp-video-msch0@ffa87000 { compatible = "rockchip,rk3399-nocp"; reg = <0x0 0xffa87000 0x0 0x400>; }; nocp\_vio0\_msch0: nocp-vio0-msch0@ffa87400 { compatible = "rockchip,rk3399-nocp"; reg = <0x0 0xffa87400 0x0 0x400>; }; nocp\_vio1\_msch0: nocp-vio1-msch0@ffa87800 { compatible = "rockchip,rk3399-nocp"; reg = <0x0 0xffa87800 0x0 0x400>; }; nocp\_cci\_msch1: nocp-cci-msch1@ffa8e000 { compatible = "rockchip,rk3399-nocp"; reg = <0x0 0xffa8e000 0x0 0x400>; }; nocp\_gpu\_msch1: nocp-gpu-msch1@ffa8e400 { compatible = "rockchip,rk3399-nocp"; reg = <0x0 0xffa8e400 0x0 0x400>; }; nocp\_hp\_msch1: nocp-hp-msch1@ffa8e800 { compatible = "rockchip,rk3399-nocp"; reg = <0x0 0xffa8e800 0x0 0x400>; }; nocp\_lp\_msch1: nocp-lp-msch1@ffa8ec00 { compatible = "rockchip,rk3399-nocp"; reg = <0x0 0xffa8ec00 0x0 0x400>; }; nocp\_video\_msch1: nocp-video-msch1@ffa8f000 { compatible = "rockchip,rk3399-nocp"; reg = <0x0 0xffa8f000 0x0 0x400>; }; nocp\_vio0\_msch1: nocp-vio0-msch1@ffa8f400 { compatible = "rockchip,rk3399-nocp"; reg = <0x0 0xffa8f400 0x0 0x400>; }; nocp\_vio1\_msch1: nocp-vio1-msch1@ffa8f800 { compatible = "rockchip,rk3399-nocp"; reg = <0x0 0xffa8f800 0x0 0x400>; }; pinctrl: pinctrl { compatible = "rockchip,rk3399-pinctrl"; rockchip,grf = <&grf>; rockchip,pmu = <&pmugrf>; #address-cells = <0x2>; #size-cells = <0x2>; ranges; gpio0: gpio0@ff720000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff720000 0x0 0x100>; clocks = <&pmucru PCLK\_GPIO0\_PMU>; interrupts = <GIC\_SPI 14 IRQ\_TYPE\_LEVEL\_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; interrupt-controller; #interrupt-cells = <0x2>; }; gpio1: gpio1@ff730000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff730000 0x0 0x100>; clocks = <&pmucru PCLK\_GPIO1\_PMU>; interrupts = <GIC\_SPI 15 IRQ\_TYPE\_LEVEL\_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; interrupt-controller; #interrupt-cells = <0x2>; }; gpio2: gpio2@ff780000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff780000 0x0 0x100>; clocks = <&cru PCLK\_GPIO2>; interrupts = <GIC\_SPI 16 IRQ\_TYPE\_LEVEL\_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; interrupt-controller; #interrupt-cells = <0x2>; }; gpio3: gpio3@ff788000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff788000 0x0 0x100>; clocks = <&cru PCLK\_GPIO3>; interrupts = <GIC\_SPI 17 IRQ\_TYPE\_LEVEL\_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; interrupt-controller; #interrupt-cells = <0x2>; }; gpio4: gpio4@ff790000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff790000 0x0 0x100>; clocks = <&cru PCLK\_GPIO4>; interrupts = <GIC\_SPI 18 IRQ\_TYPE\_LEVEL\_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; interrupt-controller; #interrupt-cells = <0x2>; }; pcfg\_pull\_up: pcfg-pull-up { bias-pull-up; }; pcfg\_pull\_down: pcfg-pull-down { bias-pull-down; }; pcfg\_pull\_none: pcfg-pull-none { bias-disable; }; pcfg\_pull\_up\_20ma: pcfg-pull-up-20ma { bias-pull-up; drive-strength = <20>; }; pcfg\_pull\_none\_20ma: pcfg-pull-none-20ma { bias-disable; drive-strength = <20>; }; pcfg\_pull\_none\_18ma: pcfg-pull-none-18ma { bias-disable; drive-strength = <18>; }; pcfg\_pull\_none\_12ma: pcfg-pull-none-12ma { bias-disable; drive-strength = <12>; }; pcfg\_pull\_up\_8ma: pcfg-pull-up-8ma { bias-pull-up; drive-strength = <8>; }; pcfg\_pull\_down\_4ma: pcfg-pull-down-4ma { bias-pull-down; drive-strength = <4>; }; pcfg\_pull\_up\_2ma: pcfg-pull-up-2ma { bias-pull-up; drive-strength = <2>; }; pcfg\_pull\_down\_12ma: pcfg-pull-down-12ma { bias-pull-down; drive-strength = <12>; }; pcfg\_pull\_none\_13ma: pcfg-pull-none-13ma { bias-disable; drive-strength = <13>; }; pcfg\_output\_high: pcfg-output-high { output-high; }; pcfg\_output\_low: pcfg-output-low { output-low; }; pcfg\_input: pcfg-input { input-enable; }; emmc { emmc\_pwr: emmc-pwr { rockchip,pins = <0 5 RK\_FUNC\_1 &pcfg\_pull\_up>; }; }; gmac { rgmii\_pins: rgmii-pins { rockchip,pins = /\* mac\_txclk \*/ <3 17 RK\_FUNC\_1 &pcfg\_pull\_none\_13ma>, /\* mac\_rxclk \*/ <3 14 RK\_FUNC\_1 &pcfg\_pull\_none>, /\* mac\_mdio \*/ <3 13 RK\_FUNC\_1 &pcfg\_pull\_none>, /\* mac\_txen \*/ <3 12 RK\_FUNC\_1 &pcfg\_pull\_none\_13ma>, /\* mac\_clk \*/ <3 11 RK\_FUNC\_1 &pcfg\_pull\_none>, /\* mac\_rxdv \*/ <3 9 RK\_FUNC\_1 &pcfg\_pull\_none>, /\* mac\_mdc \*/ <3 8 RK\_FUNC\_1 &pcfg\_pull\_none>, /\* mac\_rxd1 \*/ <3 7 RK\_FUNC\_1 &pcfg\_pull\_none>, /\* mac\_rxd0 \*/ <3 6 RK\_FUNC\_1 &pcfg\_pull\_none>, /\* mac\_txd1 \*/ <3 5 RK\_FUNC\_1 &pcfg\_pull\_none\_13ma>, /\* mac\_txd0 \*/ <3 4 RK\_FUNC\_1 &pcfg\_pull\_none\_13ma>, /\* mac\_rxd3 \*/ <3 3 RK\_FUNC\_1 &pcfg\_pull\_none>, /\* mac\_rxd2 \*/ <3 2 RK\_FUNC\_1 &pcfg\_pull\_none>, /\* mac\_txd3 \*/ <3 1 RK\_FUNC\_1 &pcfg\_pull\_none\_13ma>, /\* mac\_txd2 \*/ <3 0 RK\_FUNC\_1 &pcfg\_pull\_none\_13ma>; }; rmii\_pins: rmii-pins { rockchip,pins = /\* mac\_mdio \*/ <3 13 RK\_FUNC\_1 &pcfg\_pull\_none>, /\* mac\_txen \*/ <3 12 RK\_FUNC\_1 &pcfg\_pull\_none\_13ma>, /\* mac\_clk \*/ <3 11 RK\_FUNC\_1 &pcfg\_pull\_none>, /\* mac\_rxer \*/ <3 10 RK\_FUNC\_1 &pcfg\_pull\_none>, /\* mac\_rxdv \*/ <3 9 RK\_FUNC\_1 &pcfg\_pull\_none>, /\* mac\_mdc \*/ <3 8 RK\_FUNC\_1 &pcfg\_pull\_none>, /\* mac\_rxd1 \*/ <3 7 RK\_FUNC\_1 &pcfg\_pull\_none>, /\* mac\_rxd0 \*/ <3 6 RK\_FUNC\_1 &pcfg\_pull\_none>, /\* mac\_txd1 \*/ <3 5 RK\_FUNC\_1 &pcfg\_pull\_none\_13ma>, /\* mac\_txd0 \*/ <3 4 RK\_FUNC\_1 &pcfg\_pull\_none\_13ma>; }; }; i2c0 { i2c0\_xfer: i2c0-xfer { rockchip,pins = <1 15 RK\_FUNC\_2 &pcfg\_pull\_none>, <1 16 RK\_FUNC\_2 &pcfg\_pull\_none>; }; }; i2c1 { i2c1\_xfer: i2c1-xfer { rockchip,pins = <4 2 RK\_FUNC\_1 &pcfg\_pull\_none>, <4 1 RK\_FUNC\_1 &pcfg\_pull\_none>; }; }; i2c2 { i2c2\_xfer: i2c2-xfer { rockchip,pins = <2 1 RK\_FUNC\_2 &pcfg\_pull\_none\_12ma>, <2 0 RK\_FUNC\_2 &pcfg\_pull\_none\_12ma>; }; }; i2c3 { i2c3\_xfer: i2c3-xfer { rockchip,pins = <4 17 RK\_FUNC\_1 &pcfg\_pull\_none>, <4 16 RK\_FUNC\_1 &pcfg\_pull\_none>; }; i2c3\_gpio: i2c3\_gpio { rockchip,pins = <4 17 RK\_FUNC\_GPIO &pcfg\_pull\_none>, <4 16 RK\_FUNC\_GPIO &pcfg\_pull\_none>; }; }; i2c4 { i2c4\_xfer: i2c4-xfer { rockchip,pins = <1 12 RK\_FUNC\_1 &pcfg\_pull\_none>, <1 11 RK\_FUNC\_1 &pcfg\_pull\_none>; }; }; i2c5 { i2c5\_xfer: i2c5-xfer { rockchip,pins = <3 11 RK\_FUNC\_2 &pcfg\_pull\_none>, <3 10 RK\_FUNC\_2 &pcfg\_pull\_none>; }; }; i2c6 { i2c6\_xfer: i2c6-xfer { rockchip,pins = <2 10 RK\_FUNC\_2 &pcfg\_pull\_none>, <2 9 RK\_FUNC\_2 &pcfg\_pull\_none>; }; }; i2c7 { i2c7\_xfer: i2c7-xfer { rockchip,pins = <2 8 RK\_FUNC\_2 &pcfg\_pull\_none>, <2 7 RK\_FUNC\_2 &pcfg\_pull\_none>; }; }; i2c8 { i2c8\_xfer: i2c8-xfer { rockchip,pins = <1 21 RK\_FUNC\_1 &pcfg\_pull\_none>, <1 20 RK\_FUNC\_1 &pcfg\_pull\_none>; }; }; i2s0 { i2s0\_8ch\_bus: i2s0-8ch-bus { rockchip,pins = <3 24 RK\_FUNC\_1 &pcfg\_pull\_none>, <3 25 RK\_FUNC\_1 &pcfg\_pull\_none>, <3 26 RK\_FUNC\_1 &pcfg\_pull\_none>, <3 27 RK\_FUNC\_1 &pcfg\_pull\_none>, <3 28 RK\_FUNC\_1 &pcfg\_pull\_none>, <3 29 RK\_FUNC\_1 &pcfg\_pull\_none>, <3 30 RK\_FUNC\_1 &pcfg\_pull\_none>, <3 31 RK\_FUNC\_1 &pcfg\_pull\_none>; }; i2s\_8ch\_mclk: i2s-8ch-mclk { rockchip,pins = <4 0 RK\_FUNC\_1 &pcfg\_pull\_none>; }; }; i2s1 { i2s1\_2ch\_bus: i2s1-2ch-bus { rockchip,pins = <4 3 RK\_FUNC\_1 &pcfg\_pull\_none>, <4 4 RK\_FUNC\_1 &pcfg\_pull\_none>, <4 5 RK\_FUNC\_1 &pcfg\_pull\_none>, <4 6 RK\_FUNC\_1 &pcfg\_pull\_none>, <4 7 RK\_FUNC\_1 &pcfg\_pull\_none>; }; }; sdio0 { sdio0\_bus1: sdio0-bus1 { rockchip,pins = <2 20 RK\_FUNC\_1 &pcfg\_pull\_up>; }; sdio0\_bus4: sdio0-bus4 { rockchip,pins = <2 20 RK\_FUNC\_1 &pcfg\_pull\_up>, <2 21 RK\_FUNC\_1 &pcfg\_pull\_up>, <2 22 RK\_FUNC\_1 &pcfg\_pull\_up>, <2 23 RK\_FUNC\_1 &pcfg\_pull\_up>; }; sdio0\_cmd: sdio0-cmd { rockchip,pins = <2 24 RK\_FUNC\_1 &pcfg\_pull\_up>; }; sdio0\_clk: sdio0-clk { rockchip,pins = <2 25 RK\_FUNC\_1 &pcfg\_pull\_none>; }; sdio0\_cd: sdio0-cd { rockchip,pins = <2 26 RK\_FUNC\_1 &pcfg\_pull\_up>; }; sdio0\_pwr: sdio0-pwr { rockchip,pins = <2 27 RK\_FUNC\_1 &pcfg\_pull\_up>; }; sdio0\_bkpwr: sdio0-bkpwr { rockchip,pins = <2 28 RK\_FUNC\_1 &pcfg\_pull\_up>; }; sdio0\_wp: sdio0-wp { rockchip,pins = <0 3 RK\_FUNC\_1 &pcfg\_pull\_up>; }; sdio0\_int: sdio0-int { rockchip,pins = <0 4 RK\_FUNC\_1 &pcfg\_pull\_up>; }; }; sdmmc { sdmmc\_bus1: sdmmc-bus1 { rockchip,pins = <4 8 RK\_FUNC\_1 &pcfg\_pull\_up>; }; sdmmc\_bus4: sdmmc-bus4 { rockchip,pins = <4 8 RK\_FUNC\_1 &pcfg\_pull\_up>, <4 9 RK\_FUNC\_1 &pcfg\_pull\_up>, <4 10 RK\_FUNC\_1 &pcfg\_pull\_up>, <4 11 RK\_FUNC\_1 &pcfg\_pull\_up>; }; sdmmc\_clk: sdmmc-clk { rockchip,pins = <4 12 RK\_FUNC\_1 &pcfg\_pull\_none>; }; sdmmc\_cmd: sdmmc-cmd { rockchip,pins = <4 13 RK\_FUNC\_1 &pcfg\_pull\_up>; }; sdmmc\_cd: sdmcc-cd { rockchip,pins = <0 7 RK\_FUNC\_1 &pcfg\_pull\_up>; }; sdmmc\_wp: sdmmc-wp { rockchip,pins = <0 8 RK\_FUNC\_1 &pcfg\_pull\_up>; }; }; spdif { spdif\_bus: spdif-bus { rockchip,pins = <4 21 RK\_FUNC\_1 &pcfg\_pull\_none>; }; spdif\_bus\_1: spdif-bus-1 { rockchip,pins = <3 16 RK\_FUNC\_3 &pcfg\_pull\_none>; }; }; spi0 { spi0\_clk: spi0-clk { rockchip,pins = <3 6 RK\_FUNC\_2 &pcfg\_pull\_up>; }; spi0\_cs0: spi0-cs0 { rockchip,pins = <3 7 RK\_FUNC\_2 &pcfg\_pull\_up>; }; spi0\_cs1: spi0-cs1 { rockchip,pins = <3 8 RK\_FUNC\_2 &pcfg\_pull\_up>; }; spi0\_tx: spi0-tx { rockchip,pins = <3 5 RK\_FUNC\_2 &pcfg\_pull\_up>; }; spi0\_rx: spi0-rx { rockchip,pins = <3 4 RK\_FUNC\_2 &pcfg\_pull\_up>; }; }; spi1 { spi1\_clk: spi1-clk { rockchip,pins = <1 9 RK\_FUNC\_2 &pcfg\_pull\_up>; }; spi1\_cs0: spi1-cs0 { rockchip,pins = <1 10 RK\_FUNC\_2 &pcfg\_pull\_up>; }; spi1\_rx: spi1-rx { rockchip,pins = <1 7 RK\_FUNC\_2 &pcfg\_pull\_up>; }; spi1\_tx: spi1-tx { rockchip,pins = <1 8 RK\_FUNC\_2 &pcfg\_pull\_up>; }; }; spi2 { spi2\_clk: spi2-clk { rockchip,pins = <2 11 RK\_FUNC\_1 &pcfg\_pull\_up>; }; spi2\_cs0: spi2-cs0 { rockchip,pins = <2 12 RK\_FUNC\_1 &pcfg\_pull\_up>; }; spi2\_rx: spi2-rx { rockchip,pins = <2 9 RK\_FUNC\_1 &pcfg\_pull\_up>; }; spi2\_tx: spi2-tx { rockchip,pins = <2 10 RK\_FUNC\_1 &pcfg\_pull\_up>; }; }; spi3 { spi3\_clk: spi3-clk { rockchip,pins = <1 17 RK\_FUNC\_1 &pcfg\_pull\_up>; }; spi3\_cs0: spi3-cs0 { rockchip,pins = <1 18 RK\_FUNC\_1 &pcfg\_pull\_up>; }; spi3\_rx: spi3-rx { rockchip,pins = <1 15 RK\_FUNC\_1 &pcfg\_pull\_up>; }; spi3\_tx: spi3-tx { rockchip,pins = <1 16 RK\_FUNC\_1 &pcfg\_pull\_up>; }; }; spi4 { spi4\_clk: spi4-clk { rockchip,pins = <3 2 RK\_FUNC\_2 &pcfg\_pull\_up>; }; spi4\_cs0: spi4-cs0 { rockchip,pins = <3 3 RK\_FUNC\_2 &pcfg\_pull\_up>; }; spi4\_rx: spi4-rx { rockchip,pins = <3 0 RK\_FUNC\_2 &pcfg\_pull\_up>; }; spi4\_tx: spi4-tx { rockchip,pins = <3 1 RK\_FUNC\_2 &pcfg\_pull\_up>; }; }; spi5 { spi5\_clk: spi5-clk { rockchip,pins = <2 22 RK\_FUNC\_2 &pcfg\_pull\_up>; }; spi5\_cs0: spi5-cs0 { rockchip,pins = <2 23 RK\_FUNC\_2 &pcfg\_pull\_up>; }; spi5\_rx: spi5-rx { rockchip,pins = <2 20 RK\_FUNC\_2 &pcfg\_pull\_up>; }; spi5\_tx: spi5-tx { rockchip,pins = <2 21 RK\_FUNC\_2 &pcfg\_pull\_up>; }; }; tsadc { otp\_gpio: otp-gpio { rockchip,pins = <1 6 RK\_FUNC\_GPIO &pcfg\_pull\_none>; }; otp\_out: otp-out { rockchip,pins = <1 6 RK\_FUNC\_1 &pcfg\_pull\_none>; }; }; uart0 { uart0\_xfer: uart0-xfer { rockchip,pins = <2 16 RK\_FUNC\_1 &pcfg\_pull\_up>, <2 17 RK\_FUNC\_1 &pcfg\_pull\_none>; }; uart0\_cts: uart0-cts { rockchip,pins = <2 18 RK\_FUNC\_1 &pcfg\_pull\_none>; }; uart0\_rts: uart0-rts { rockchip,pins = <2 19 RK\_FUNC\_1 &pcfg\_pull\_none>; }; }; uart1 { uart1\_xfer: uart1-xfer { rockchip,pins = <3 12 RK\_FUNC\_2 &pcfg\_pull\_up>, <3 13 RK\_FUNC\_2 &pcfg\_pull\_none>; }; }; uart2a { uart2a\_xfer: uart2a-xfer { rockchip,pins = <4 8 RK\_FUNC\_2 &pcfg\_pull\_up>, <4 9 RK\_FUNC\_2 &pcfg\_pull\_none>; }; }; uart2b { uart2b\_xfer: uart2b-xfer { rockchip,pins = <4 16 RK\_FUNC\_2 &pcfg\_pull\_up>, <4 17 RK\_FUNC\_2 &pcfg\_pull\_none>; }; }; uart2c { uart2c\_xfer: uart2c-xfer { rockchip,pins = <4 19 RK\_FUNC\_1 &pcfg\_pull\_up>, <4 20 RK\_FUNC\_1 &pcfg\_pull\_none>; }; }; uart3 { uart3\_xfer: uart3-xfer { rockchip,pins = <3 14 RK\_FUNC\_2 &pcfg\_pull\_up>, <3 15 RK\_FUNC\_2 &pcfg\_pull\_none>; }; uart3\_cts: uart3-cts { rockchip,pins = <3 16 RK\_FUNC\_2 &pcfg\_pull\_none>; }; uart3\_rts: uart3-rts { rockchip,pins = <3 17 RK\_FUNC\_2 &pcfg\_pull\_none>; }; }; uart4 { uart4\_xfer: uart4-xfer { rockchip,pins = <1 7 RK\_FUNC\_1 &pcfg\_pull\_up>, <1 8 RK\_FUNC\_1 &pcfg\_pull\_none>; }; }; uarthdcp { uarthdcp\_xfer: uarthdcp-xfer { rockchip,pins = <4 21 RK\_FUNC\_2 &pcfg\_pull\_up>, <4 22 RK\_FUNC\_2 &pcfg\_pull\_none>; }; }; pwm0 { pwm0\_pin: pwm0-pin { rockchip,pins = <4 18 RK\_FUNC\_1 &pcfg\_pull\_none>; }; vop0\_pwm\_pin: vop0-pwm-pin { rockchip,pins = <4 18 RK\_FUNC\_2 &pcfg\_pull\_none>; }; vop1\_pwm\_pin: vop1-pwm-pin { rockchip,pins = <4 18 RK\_FUNC\_3 &pcfg\_pull\_none>; }; }; pwm1 { pwm1\_pin: pwm1-pin { rockchip,pins = <4 22 RK\_FUNC\_1 &pcfg\_pull\_none>; }; }; pwm2 { pwm2\_pin: pwm2-pin { rockchip,pins = <1 19 RK\_FUNC\_1 &pcfg\_pull\_none>; }; }; pwm3a { pwm3a\_pin: pwm3a-pin { rockchip,pins = <0 6 RK\_FUNC\_1 &pcfg\_pull\_none>; }; }; pwm3b { pwm3b\_pin: pwm3b-pin { rockchip,pins = <1 14 RK\_FUNC\_1 &pcfg\_pull\_none>; }; }; edp { edp\_hpd: edp-hpd { rockchip,pins = <4 23 RK\_FUNC\_2 &pcfg\_pull\_none>; }; }; hdmi { hdmi\_i2c\_xfer: hdmi-i2c-xfer { rockchip,pins = <4 17 RK\_FUNC\_3 &pcfg\_pull\_none>, <4 16 RK\_FUNC\_3 &pcfg\_pull\_none>; }; hdmi\_cec: hdmi-cec { rockchip,pins = <4 23 RK\_FUNC\_1 &pcfg\_pull\_none>; }; }; pcie { pcie\_clkreqn: pci-clkreqn { rockchip,pins = <2 26 RK\_FUNC\_2 &pcfg\_pull\_none>; }; pcie\_clkreqnb: pci-clkreqnb { rockchip,pins = <4 24 RK\_FUNC\_1 &pcfg\_pull\_none>; }; pcie\_clkreqn\_cpm: pci-clkreqn-cpm { /\* \* Since our pcie doesn't support \* ClockPM(CPM), we want to hack this as \* gpio, so the EP could be able to \* de-assert it along and make ClockPM(CPM) \* work. \*/ rockchip,pins = <2 26 RK\_FUNC\_GPIO &pcfg\_pull\_none>; }; pcie\_clkreqnb\_cpm: pci-clkreqnb-cpm { rockchip,pins = <4 24 RK\_FUNC\_GPIO &pcfg\_pull\_none>; }; }; }; rockchip\_suspend: rockchip-suspend { compatible = "rockchip,pm-rk3399"; status = "disabled"; rockchip,sleep-debug-en = <0>; rockchip,virtual-poweroff = <0>; rockchip,sleep-mode-config = < (0 | RKPM\_SLP\_ARMPD | RKPM\_SLP\_PERILPPD | RKPM\_SLP\_DDR\_RET | RKPM\_SLP\_PLLPD | RKPM\_SLP\_OSC\_DIS | RKPM\_SLP\_CENTER\_PD | RKPM\_SLP\_AP\_PWROFF ) >; rockchip,wakeup-config = < (0 | RKPM\_GPIO\_WKUP\_EN ) >; }; };
bigood
2024年4月25日 14:06
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